The present invention relates to a semiconductor memory device and the manufacturing method thereof, and more particularly, to the structure of the node electrode of a dynamic random access memory (DRAM) including a memory cell consisting of one MOS transistor and one stacked capacitor and to the manufacturing method thereof.
Description of the Prior Art
DRAMs having memory cells each consisting of one MOS transistor and one capacitor have been developed with the intention of reducing the occupancy area of the memory cell and to augment the capacitance of the capacitor to a maximum extent possible. The reduction of the occupancy area of the memory cell has mainly been realized by assigning a fine geometry to the MOS transistor, but the occupancy area of the capacitor has also been reduced accordingly. The capacitors have been developed from the planar type through the trench type to the stacked type which has a vertical structure.
In a DRAM which includes a stacked type capacitor, the MOS transistor is constituted by a gate electrode which serves as both of a gate insulating film and a word line, a node diffused layer, and a bit diffused layer, and the capacitor is constituted by a node electrode which is connected to the node diffused layer via a node contact hole, a capacitor insulating film, and a cell plate electrode. One of the methods for increasing the capacitance of such a DRAM is to increase the facing area of the node electrode and the cell plate electrode. This is realized mainly by increasing the surface area of the node electrode. As a method for accomplishing this, there is a method of using a node electrode of a fin structure, for example, as reported in IEDM Tech. Dig., 1988, pp. 592-595 by T. Ema, et al. In this report there is reported a structure in which a bit line is formed in the tip layer of a stacked type capacitor and a structure in which a stacked type capacitor is formed above a bit line. A method of forming a memory cell for a DRAM having a node electrode of a fin structure, with the former structure in the report as an example, will be described below.
First, a field oxide film is formed on the surface of a p-type silicon substrate, and forms a transistor consisting of a gate electrode which serves for both of a gate oxide film and a word line, an n-type node diffused layer, and an n-type bit diffused layer. Then, a first interlayer insulating film is deposited all over the surface. At least the surface of the interlayer insulating film is formed of a silicon nitride film. Subsequently, a first silicon oxide film, an n-type first polycrystalline silicon film, and a second silicon oxide film are deposited sequentially.
Next, a node contact hole reaching the node diffused layer is opened by sequentially etching the second silicon oxide film, the first polycrystalline silicon film, the first silicon oxide film, and the first interlayer insulating film. After removing the photoresist film, an n-type second polycrystalline silicon film is deposited all over the surface. Next, using a photoresist provided in the region reserved for a node electrode as the mask, the second polycrystalline silicon film, the second silicon oxide film, the first polycrystalline silicon film, and the first silicon oxide film are removed sequentially by anisotropic etching such as RIE. After removal of the photoresist film, the second silicon oxide film in between the second polycrystalline silicon film and the first polycrystalline silicon film, and the first silicon oxide film in between the first polycrystalline silicon film and the first interlayer insulating film are removed by wet etching that uses hydrofluoric acid, completing a node electrode of fin structure.
Next, a capacitor insulating film is deposited all over the surface. An n-type third polycrystalline silicon film is deposited all over the surface, and a cell plate electrode is formed by etching the film. The exposed capacitor insulating film is removed by etching that uses the cell plate electrode as the mask, completing a stacked type capacitor. Next, a second interlayer insulating film is deposited all over the surface, and a bit contact hole is opened by sequentially etching the second interlayer insulating film and the first interlayer insulating film on the bit diffused layer. A bit line which is connected to the bit diffused layer via the bit contact hole is formed, completing a memory cell of the DRAM.
However, a method such as in the above which attempts to increase the surface area of the node electrode by means of the fin structure has a working process which is complicated and difficult. Namely, in realizing the structure of the node electrode, the mechanical strength of the node electrode is deteriorated in the stage of removing by etching the silicon oxide film placed between the polycrystalline silicon films, and the processes of washing and the like will be difficult.